The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks

Two important optimizations within the FPGA design process, C-slow retiming and datapath placement, offer significant benefits for designers. Many have advocated and implemented tools to use these techniques in both automatic and semiautomatic manner [1][2][5] but they have not made their way into conventional FPGA toolflo ws. C-slow retiming[3] is a method of accelerating computations that include feedback loops. Instead of having a single instance of the computation, the feedback loop is pipelined so thatC separate instances are all calculated simultaneously. This allows fine grained pipelining to occur even in designs that include feedback loops, such as single round cryptographic implementations or microprocessors. Done properly, it imposes a significant but not imposing latency penalty for single computations while offering huge increases in throughput. Datapath placement is simply constructing the design in a manner that accounts for the higher level data flo ws. This offers several benefits, including improved performance[4], more physically compact designs, shorter wires, and faster place and route times when the FPGA is heavily utilized. Even for designs with less structure which are amenable to simulated annealing, datapath placement may still offer a significant benefit. To clearly demonstrate the importance of these optimizations we have hand-modified three computational benchmarks which represent significant themes within FPGA computation: Rijndael/AES encryption, Smith/Waterman, and a simplified 32-bit microprocessor datapath. All three represent significantly different modes of computation within FPGAs, but all gain significantly from the use of these techniques. The first, Rijndael encryption, uses bit and byte mixing and small table lookups on 128b datapaths to implement encryption. Because this has been adopted as the DES replacement by the US Government, it will undoubtedly be the most widely deployed block cipher over the next twenty years. The second, Smith/Waterman, is a commonly used systolic sequence matching routine for bioinformatics. It relies on 16 bit additions and clearly demonstrates the benefits of specialization. The final benchmark is the datapath for a simplified, multithreaded, 32 bit processor. It uses a radically simplified MIPS instruction set. It is typical of full processor implementations with simplified control. All implementations were targeted toward Xilinx Spartan II series, a Virtex [6] derived FPGA intended for low cost applications. The Spartan II was selected for two reasons: its modern architecture has features needed to make C-slow retiming effective (Embedded memories, LUTs as shift registers) and to demonstrate the capabilities of the current low-cost FPGAs. We are able to achieve >100 MHz operation with throughput speedups of 2x or greater on all three benchmark circuits by applying these optimizations together. All designs were input as schematics using Xilinx Foundation 4.1 with RLOCs used to place almost every block (except for a few control signals which are better handled by simulated annealing). All compilation was performed on a Pentium II 300 with 256 MB of memory running Windows 2000. Timing results are from the static timing analysis, worst case process corner for the -5 speed grade part. The place and route effort was set to maximum for all runs, but no other constraints were imposed on the toolflo w.